EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGA
Jaya Koshta, Kavita Khare and M.K Gupta Maulana Azad National Institute of Technology, Bhopal
Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA
HEVC, motion estimation, sum of absolute difference, parallel prefix adders, Brent Kung Adder.
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http://aircconline.com/vlsics/V10N2/10219vlsi01.pdf
FPGA IMPLEMENTATION OF HUANG HILBERT TRANSFORM FOR CLASSIFICATION OF EPILEPTIC SEIZURES USING ARTIFICIAL NEURAL NETWORK
G.Deepika1 and K.S.Rao2 ,1Asso.Prof at RRS college of Engg,India , 2Anurag group of Institutions, Hyderabad
The most common brain disorders due to abnormal burst of electrical discharges are termed as Epileptic seizures. This work proposes an efficient approach to extract the features of epileptic seizures by decomposing EEG into band limited signals termed as IMF’s by empirical decomposition EMD. Huang Hilbert Transform is applied on these IMF’s for calculating Instantaneous frequencies and are classified using artificial neural network trained by Back propagation algorithm. The results indicate an accuracy of 97.87%. The algorithm is implemented using Verilog HDL on Zynq 7000 family FPGA evaluation board using Xilinx vivado 2015.2 version.
EEG, IMF,EMD
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http://aircconline.com/vlsics/V10N3/10319vlsi02.pdf
DUTY CYCLE CORRECTOR USING PULSE WIDTH MODULATION
Meghana Patil1 , Dr. Kiran Bailey2 and Rajanikanth Anuvanahally3 1,2BMSCE, India 3Senior Member IEEE, India
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW
DCC, Integrator, Control voltage generator, frequency range
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: http://aircconline.com/vlsics/V10N3/10319vlsi01.pdf
DESIGN AND IMPLEMENTATION OF COMBINED PIPELINING AND PARALLEL PROCESSING ARCHITECTURE FOR FIR AND IIR FILTERS USING VHDL
Jacinta Potsangbam1 and Manoj Kumar2 1,2 National Institute of Technology, India
Along with the advancement in VLSI (Very Large Scale Integration) technology, the implementation of Finite impulse response (FIR) filters and Infinite impulse response (IIR) filters with enhanced speed has become more demanding. This paper aims at designing and implementing a combined pipelining and parallel processing architecture for FIR and IIR filter using VHDL (Very High Speed Integrated Circuit Hardware Descriptive Language) to reduce the power consumption and delay of the filter. The proposed architecture is compared with the original FIR and IIR filter respectively in terms of speed, area, and power. Also, the proposed architecture is compared with existing architectures in terms of delay. The implementation is done by using VHDL codes. FIR and IIR filters structures are implemented at 1200 KHz clock frequency. Synthesis and simulation have been accomplished on Artix-7 series FPGA, target device (xc7a200tfbg676) (speed grade -1) using VIVADO 2016.3.
DSP, FIR, FPGA, IIR, MIMO.
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http://aircconline.com/vlsics/V10N4/10419vlsi01.pdf
DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR
P. Indira1 , M. Kamaraju2 and Ved Vyas Dwivedi3 , 1,3CU Shah University, Wadhwan, India , 2 JNT University, Kakinada, India
Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work. . The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fundamental functional blocks of the processor include Input/Output blocks, configurable logic blocks, Block RAM, and Digital clock Manager and each block permits to connect to multiple sources for the routing. The Auxiliary units enhance the performance of the processor. The comparative study elevates the designed model in terms of Area, Power and Frequency. MATLAB2D/3D graphs represents the relationship among various parameters of this pipelining. In this pipeline model, it consumes very less power (0.129 W),path delay (11.180 ns) and low LUT utilization (421). Similarly, the proposed model achieves better frequency increase (285.583 Mhz.), which obtained better results compared to other models.
MATLAB, SPARTAN3E, MIPS RISC processor, Xilinx, Digital Clock Manager
For More Details :
http://aircconline.com/vlsics/V10N5/10519vlsi01.pdf